This invention relates to digital loop circuits (i.e., phase-locked loops or delay-locked loops) having reduced complexity, and particularly to such loop circuits for use in a programmable logic device.
It is known to incorporate phase-locked loop (“PLL”) and delay-locked loop (“DLL”) circuitry on programmable logic devices (“PLDs”). For example, it has become common for PLDs to accommodate various input/output standards, some of which require very accurate high-speed clocks. One way of providing such clocks is to provide loop circuitry on the PLD. Although the discussion that follows may concentrate primarily on PLLs, the present invention is applicable equally to DLLs.
A basic PLL includes a phase-frequency detector (“PFD”), a charge pump, a loop filter and a voltage-controlled oscillator (“VCO”), connected in series. The input or reference frequency is one input to the PFD. The output of the VCO, which is the output of the PLL, is also fed back to another input of the PFD. If the feedback signal is not locked to the input reference signal, then the PFD output will be a signal (e.g., voltage) whose sign is indicative of whether the output leads or lags and whose magnitude is indicative of the amount of lead or lag. That signal is filtered by the charge pump and loop filter and is input to the VCO, causing the output frequency to change. Eventually, the output signal will lock to the phase of the input reference signal. In this simple example, the output signal also will lock to the frequency of the input reference signal, but in many PLLs, counters on the input and output of the PLL may be used to divide the input frequency, while a counter/divider in the feedback loop is used to multiply the input frequency. Thus the frequency of the output signal can be any rational multiple of the input frequency, but will be phase-locked to the input frequency.
The loop filter of a PLL also may have separate proportional and integral paths which may operate differently at different data rates or frequency ranges.
DLLs operate similarly, except that in a DLL, the phase-frequency detector normally found in a PLL is replaced with phase detector, and the VCO normally found in a PLL is replaced with a variable delay line.
Loop circuits are thus relatively large and complex circuits, and providing loop circuits on PLDs therefore either adds significant area to the PLD, or takes away area that could be used for programmable logic circuitry in a PLD of a given size. This is of further concern because the loop circuits that are provided may not be used in a particular user design, so that, as far as that user is concerned, the loop circuitry is simply wasted. Therefore, it would be desirable to be able to minimize the size and complexity of loop circuits.